Posts

Showing posts from September, 2016

Cache policies and its details

Source : http://web.cs.iastate.edu/~prabhu/Tutorial/CACHE/interac.html Reads dominate processor cache accesses. All instruction accesses are reads, and most instructions do not write to memory. The block can be read at the same time that the tag is read and compared, so the block read begins as soon as the block address is available. If the read is a miss, there is no benefit - but also no harm; just ignore the value read. The read policies are: 1. Read Through  -   reading a word from main memory to CPU 2. No Read Through -  reading a block from main memory to cache and then from cache to CPU Such is not the case for writes. Modifying a block cannot begin until the tag is checked to see if the address is a hit.  Also, the processor specifies the size of the write, usually between 1 and 8 bytes; only that portion of the block can be  changed. In contrast, reads can access more bytes than necessary without a problem.  The  write policies    on write  hit  often distinguish cache